1. Field of the Invention
The present invention relates generally to copper interconnects and semiconductor manufacturing process. More particularly, the present invention relates to an improved copper dual damascene process, which is particularly suited for a copper dual damascene process utilizing a metal hard mask and is capable of solving undesired recess defects near a lower wiring layer caused by misalignment between a via hole and the lower wiring layer. The aforesaid recess defect is etched through a capping layer that caps the lower wiring layer and into a low-k dielectric layer that encapsulates the lower wiring layer.
2. Description of the Prior Art
Damascene interconnect processes incorporated with copper are known in the art, which are also referred to as “copper damascene processes” in the semiconductor industry. The copper damascene processes provide a solution to form a conductive wire coupled with an integral via plug without the need of dry etching copper. Either a single damascene or a dual damascene structure is used to connect devices and/or wires of an integrated circuit. Generally, the dual damascene process encompasses trench-first, via-first, partial-via-first, and self-aligned processes.
FIGS. 1-5 are schematic, cross-sectional diagrams showing a conventional partial-via-first dual damascene process. As shown in FIG. 1, a substrate 1 having thereon a base layer or a lower low-k dielectric layer 10 is provided. A lower copper wiring 12 is inlaid into the lower low-k dielectric layer 10. The lower copper wiring 12 and the low-k dielectric layer 10 are covered with a lower cap layer 14. A low-k dielectric layer 16, a silicon oxide cap layer 18, a metal hard mask layer 20 and a bottom anti-reflective coating (BARC) layer 22 are sequentially deposited on the lower cap layer 14. A layer of photoresist (Trench Photo) 30 having a trench opening 32 therein is formed on the BARC layer 22.
Subsequently, as shown in FIG. 2, a dry etching process is carried out. A trench recess 36 is etched into the metal hard mask layer 20 and the silicon oxide cap layer 18 through the trench opening 32. The dry etching stops on the silicon oxide cap layer 18. The remaining photoresist 30 and BARC layer 22 are then stripped off.
As shown in FIG. 3, another BARC layer 38 is coated over the substrate 1 and fills the trench recess 36. A layer of photoresist (Via Photo) 40 is then formed on the BARC layer 38. The photoresist layer 40 has a via opening 42 patterned by using conventional lithographic methods. The via opening 42 is situated directly above the trench recess 36.
Thereafter, using the photoresist layer 40 as an etching hard mask, the BARC layer 38, the silicon oxide cap layer 18, and the lower low-k dielectric layer 16 are etched through the via opening 42, thereby forming a partial via feature 46 in an upper portion of the dielectric layer 16. As shown in FIG. 4, the remaining photoresist layer 40 and the BARC layer 38 are stripped off by using oxygen plasma, thereby exposing the remaining metal hard mask layer 20.
As shown in FIG. 5, using the metal hard mask layer 20 as an etching hard mask, a dry etching is performed to etch away the exposed silicon oxide cap layer 18 and the lower low-k dielectric layer 16 simultaneously through the trench recess 36 and the partial via 46, thereby forming a dual damascene opening 50 comprising a trench opening 56 and a via opening 66. This dry etching stops on the lower cap layer 14.
As shown in FIG. 6, a so-called liner removal step or LRM step is carried out to remove the exposed lower cap layer 14 from the via opening 66, thereby exposing the lower copper wiring 12. The subsequent steps for forming an upper damascene wiring structure including, for example, deposition of barrier and plating of copper are known in the art and are therefore omitted. The aforesaid LRM step usually uses a plasma source comprising hydrogen-containing carbon fluoride such as CH2F2 or CHF3.
However, as the critical dimensions of semiconductor integrated circuit devices shrink, the misalignment between the via opening 66 of the dual damascene opening 50 and the lower copper wiring 12 becomes worse. As shown in FIG. 7 and FIG. 8, when misalignment occurs, the low-k dielectric layer 10 that encapsulates the lower copper wiring 12 is recess etched in the aforesaid LRM step after the overlying cap layer 14 is etched through. Therefore, an undesired recess defect 80 forms next to the lower copper wiring 12. Such recess defect 80 becomes problematic when performing the following barrier deposition because the barrier cannot uniformly deposit into the recess defect 80, thus adversely affecting the performance and reliability of the semiconductor integrated circuit devices. Another drawback is that the use of hydrogen-containing carbon fluoride such as CH2F2 or CHF3 in the aforesaid LRM step results in residues that are difficult to be removed. It is believed that such residues include organic meal substances derived from the plasma gas and the metal hard mask.
U.S. Pat. No. 6,905,968 discloses a process for selectively etching dielectric structure comprising a lower layer of undoped silicon oxide or F-doped silicon oxide and an upper layer of C, H-doped silicon oxide (k=2.5˜3) in order to avoid the use of an etch stop layer between the lower layer and the upper layer. The dielectric structure is etched in a plasma-etching step, which plasma-etching step is conducted using a plasma source gas that comprises nitrogen atoms and fluorine atoms. The plasma source gas can comprise a gaseous species that comprises one or more nitrogen atoms and one or more fluorine atoms (e.g., NF3). The plasma source gas can comprise (a) a gaseous species that comprises one or more nitrogen atoms (e.g., N2) and (b) a gaseous species that comprises one or more fluorine atoms (e.g., a fluorocarbon gas such as CF4). U.S. Pat. No. 6,905,968 teaches that the cap layer exposed by the via opening is removed by using CH2F2 or CHF3 plasma.
In light of the above, there is a need in this industry to provide an improved method of forming dual damascene structure in the fabrication of integrated circuits, which is capable of solving the aforesaid problems.